The present invention relates to a semiconductor integrated circuit, particularly to a technique to be effectively used for a semiconductor integrated circuit using a small-amplitude interface such as a stub series terminated logic (SSTL) for 3.3 V.
The present inventor considers that a frequency of 60 MHz to 100 MHz at most is the limit of performance as a data transfer frequency because irregular reflection occurs at both-ends of a signal transmission line in the case of a TTL (Transistor-Transistor Logic) or CMOS signal widely used as an interface between CMOS (Complementary Metal-Oxide Semiconductor) integrated circuits. In the case of the SSTL or a GTL (Gunning Transceiver Logic), however, the data transfer frequency is raised by connecting a terminating resistor to the end of a signal transmission line to prevent reflection of waveforms. In this case, the signal amplitude is set at approx. 0.8 V though the operating voltage of a semiconductor integrated circuit is 3.3 V. For the SSTL, there is the Electronic-Industries-Association-of-Japan Standards EIAJ ED-5512 (standard functional specifications of stub series terminated logics (SSTL-3) for 3.3 V) established in March, 1996. For the GTL, U.S. Pat. No. 5,023,488 (Jan. 11, 1991) is an example.